1. Field of the Invention
This invention relates to an address translation register control device which makes possible extremely flexible shared control of the address translation register in a multiprocessor system.
2. Description of the Prior Art
Address translation registers are registers which load and retain mapping data of virtual and physical space (which are necessary in translating virtual addresses into physical addresses) from memory page tables, etc., and they are used for accelerating address translation, etc. Also, with address translation register control systems of conventional multiprocessor systems, a "master/slave" system in which the processors are logically divided up into master processors and slave processors is employed. In the master/slave system, the slave processor is forced to share the address translation register used by the master processor.
With the aforementioned conventional address translation register control system, the address translation register used in master processor operation tasks can be used in other tasks, which are slave processor operation tasks.
However, since master processors are not capable of independently sharing other address translation registers (ex: the case mentioned above), as long as the slave processor continues to use the address translation register used in master processor operation tasks, it was not possible to convert tasks executed by the master processor into different tasks and thereby make use of other address translation registers. Because of this type of restriction, the processing efficiency of the multiprocessor system (which makes use of a combination of address translation registers) could not be improved.